ITC 2016 Keynote Speaker: Walden C. Rhines, Chairman and Chief Executive Officer, Mentor Graphics

View Dr. Rhines’ keynote address, The Business of Test: Test and Semiconductor Economics
presented at the Plenary Session of ITC, November 15, 2016 at 9 am.

Test methodology changes have historically been driven largely by necessity—critical needs for cost reduction or quality improvements. This history makes possible the prediction of future changes. Dr. Rhines will review the photo-rhinesdriving forces for prior discontinuities in design-for-test, analyze the rates of adoption of new test methodologies, and discuss the likely forces that will change our test priorities in the future.

Walden C. Rhines is Chairman and Chief Executive Officer of Mentor Graphics, a leader in worldwide electronic design automation with revenue of $1.2 billion in 2015. During his tenure at Mentor Graphics, revenue has nearly quadrupled and Mentor has grown the industry’s number one market share solutions in four of the ten largest product segments of the EDA industry. He joined Mentor in 1993 from Texas Instruments (TI) where he was most recently Executive Vice President in charge of TI’s semiconductor business. Rhines has served five terms as Chairman of the Electronic Design Automation Consortium. He is also a board member of the Semiconductor Research Corporation and First Growth Children and Family Charities. He received aBSE degree from the University of Michigan, an MS and Ph.D. from Stanford University, an MBA from Southern Methodist University and Honorary Doctor of Technology degrees from Nottingham Trent University and the University of Florida.

ITC 2016 Wednesday Keynote Speaker: Professor Rob A. Rutenbar, University of Illinois, Urbana-Champaign

View Prof. Rutenbar’s Wednesday keynote address, Hardware Inference Accelerators for Machine Learning  presented Wednesday, November 16, 2016 at 4:30 pm. This was a special keynote in honor of Professor Edward J. McCluskey

Machine learning (ML) technologies have revolutionized the ways in which we interact with large-scale, imperfect, real-world data. As a result, there is rising interest in opportunities to implement ML efficiently in custom hardware. photo-rutenbarWe have designed hardware for one broad class of ML techniques: Inference on Probabilistic Graphical Models (PGMs). In these graphs, labels on nodes encode what we know and “how much” we believe it; edges encode belief relationships among labels; statistical inference answers questions such as “if we observe some of the labels in the graph, what are most likely labels on the remainder?” These problems are interesting because they can be very large (e.g., every pixel in an image is one graph node) and because we need answers very fast (e.g., at video frame rates). Inference done as iterative Belief Propagation (BP) can be efficiently implemented in hardware, and we demonstrate several examples from current FPGA prototypes. We have the first configurable, scalable parallel architecture capable of running a range of standard vision benchmarks, with speedups up to 40X over conventional software. We also show that BP hardware can be made remarkably tolerant to the low-level statistical upsets expected in end-of-Moore’s-Law nanoscale silicon and post-silicon circuit fabrics, and summarize some effective resilience mechanisms in our prototypes.

ITC 2016 Thursday Keynote Speaker: Ken Hansen, CEO, Semiconductor
Research Corporation

View Mr. Hansen’s keynote address, Addressing Semiconductor Industry Needs: Defining the Future Through Creative, Exciting Research
It was presented Thursday, November 17, 2016 at 11:00 am

In the history of the semiconductor industry, there has been no other period in time with as much uncertainty in the way forward. But with uncertainty comes great opportunity. There is a need for transformative innovation fueled by breakthrough research to reinvigorate the growth of the industry. This talk will identify some of the new exciting challenges the industry is facing and research areas where investment is needed to address them. Systems of the future —autonomous vehicles, internet of things, self-adaptive configurations modeled on biology—will require advanced techniques to test them, secure them, reduce their power, and produce them without error. This increase in complexity coupled, with a decreasing ability to rely on deterministic circuits, requires new approaches to be created by cross-disciplinary teams co-optimizing across the entire design hierarchy space.